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7.3.1 User Data (UD) Page Description
This is the user data page in the information block. The page can be erased and written by software. The
page is erased by the ERASEPAGE command of the MSC_WRITECMD register. Note that the page is
not erased by a device erase operation. The device erase operation is described in Section 6.4 (p. 23) .
7.3.2 Lock Bits (LB) Page Description
This page contains the following information:
? Main block Page Lock Words (PLWs)
? User data page Lock Word (ULWs)
? Debug Lock Word (DLW)
The words in this page are organized as shown in Table 7.2 (p. 29) :
Table 7.2. Lock Bits Page Structure
127
126
N
…
1
0
DLW
ULW
PLW[N]
…
PLW[1]
PLW[0]
There are 32 page lock bits per page lock word (PLW). Bit 0 refers to the first page and bit 31 refers
to the last page within a PLW. Thus, PLW[0] contains lock bits for page 0-31 in the main block, PLW[1]
contains lock bits for page 32-63 etc. A page is locked when the bit is 0. A locked page cannot be erased
or written.
Note
Trying to write to a locked page before writing to a page which is not locked will write the
data that was attempted to write in the locked page. The recommended procedure if to
perform the write twice.
Word 127 is the debug lock word (DLW). Bit 0 of this word is the debug lock bit. If this bit is 1, then
debug access is enabled. Debug access to the core is disabled from power-on reset until the DLW is
evaluated immediately before the Cortex-M3 starts execution of the user application code. If the bit is
0, then debug access to the core remains blocked.
Word 126 is the user page lock word (ULW). Bit 0 of this word is the page lock bit. The lock bits can
be reset by a device erase operation initiated from the Authentication Access Port (AAP) registers. The
AAP is described in more detail in Section 6.4 (p. 23) . Note that the AAP is only accessible from the
debug interface, and cannot be accessed from the Cortex-M3 core.
7.3.3 Device Information (DI) Page
This read-only page holds oscillator, DAC and ADC calibration data from the production test as well as
an unique device ID. The page is further described in Section 5.6 (p. 21) .
7.3.4 Device Revision
The device revision number is read from the ROM Table. The Revision number is extracted from the
PID2 and PID3 registers, as illustrated in Figure 7.1 (p. 30) .The Rev[7:4] and Rev[3:0] must be
combined to form the complete revision number Revision[7:0].
2011-04-12 - d0001_Rev1.10
29
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